CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
Lois Orosa, Yaohua Wang, Mohammad Sadrosadati, Jeremie S. Kim, Minesh Patel, Ivan Puddu, Haocong Luo, Kaveh Razavi, Juan Gómez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Saugata Ghose, Onur Mutlu
Abstract
DRAM is the dominant main memory technology used in modern computing systems. Computing systems implement a memory controller that interfaces with DRAM via DRAM commands. DRAM executes the given commands using internal components (e.g., access transistors, sense amplifiers) that are orchestrated by DRAM internal timings, which are fixed for each DRAM command. Unfortunately, the use of fixed internal timings limits the types of operations that DRAM can perform and hinders the implementation of new functionalities and custom mechanisms that improve DRAM reliability, performance and energy. To overcome these limitations, we propose enabling programmable DRAM internal timings for controlling in-DRAM components.
To this end, we design CODIC, a new low-cost DRAM substrate that enables fine-grained control over four previously fixed internal DRAM timings that are key to many DRAM operations. We implement CODIC with only minimal changes to the DRAM chip and the DDRx interface. To demonstrate the potential of CODIC, we propose two new CODIC-based security mechanisms that outperform state-of-the-art mechanisms in several ways: (1) a new DRAM Physical Unclonable Function (PUF) that is more robust and has significantly higher throughput than state-of-the-art DRAM PUFs, and (2) the first cold boot attack prevention mechanism that does not introduce any performance or energy overheads at runtime.
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Cited by top-tier papers9
- A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chipsand Implications on Future Attacks and DefensesLois Orosa, Abdullah Giray Yaglikçi, Haocong Luo, Ataberk Olgun et al.MICRO 2021 · 74 citations
- QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM ChipsAtaberk Olgun, Minesh Patel, Abdullah Giray Yaglikçi, Haocong Luo et al.ISCA 2021 · 49 citations
- HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM ChipsAbdullah Giray Yaglikçi, Ataberk Olgun, Minesh Patel, Haocong Luo et al.MICRO 2022 · 43 citations
- FracDRAM: Fractional Values in Off-the-Shelf DRAMFei Gao, Georgios Tziantzioulis, David WentzlaffMICRO 2022 · 22 citations
- DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number GeneratorsF. Nisa Bostanci, Ataberk Olgun, Lois Orosa, Abdullah Giray Yaglikçi et al.HPCA 2022 · 19 citations
Builds on6
- TRRespass: Exploiting the Many Sides of Target Row RefreshPietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen et al.S&P 2020 · 274 citations
- SIMDRAM: a framework for bit-serial SIMD processing using DRAMNastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio, João Dinis Ferreira et al.ASPLOS 2021 · 182 citations
- Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation TechniquesJeremie S. Kim, Minesh Patel, Abdullah Giray Yaglikçi, Hasan Hassan et al.ISCA 2020 · 161 citations
- FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and CachingYaohua Wang, Lois Orosa, Xiangjun Peng, Yang Guo et al.MICRO 2020 · 72 citations
- SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile ProcessorsJawad Haj-Yahya, Mohammed Alser, Jeremie S. Kim, Abdullah Giray Yaglikçi et al.ISCA 2020 · 48 citations
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