Unifying Static and Dynamic Intermediate Languages for Accelerator Generators
Caleb Kim, Pai Li, Anshuman Mohan, Andrew Butt, Adrian Sampson, Rachit Nigam
摘要
Compilers for accelerator design languages (ADLs) translate high-level languages into application-specific hardware. ADL compilers rely on a hardware control interface to compose hardware units. There are two choices: static control, which relies on cycle-level timing; or dynamic control, which uses explicit signalling to avoid depending on timing details. Static control is efficient but brittle; dynamic control incurs hardware costs to support compositional reasoning. Piezo is an ADL compiler that unifies static and dynamic control in a single intermediate language (IL). Its key insight is that the IL’s static fragment is a refinement of its dynamic fragment: static code admits a subset of the run-time behaviors of the dynamic equivalent. Piezo can optimize code by combining facts from static and dynamic submodules, and it opportunistically converts code from dynamic to static control styles. We implement Piezo as an extension to an existing dynamic ADL compiler, Calyx. We use Piezo to implement a frontend for an existing ADL, a systolic array generator, and a packet-scheduling hardware generator to demonstrate its optimizations and the static–dynamic interactions it enables.
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引用它的顶会 Paper2
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- Anvil: A General-Purpose Timing-Safe Hardware Description LanguageJason Zhijingcheng Yu, Aditya Ranjan Jha, Umang Mathur, Trevor E. Carlson 等ASPLOS 2026
它引用的顶会 Paper7
- Predictable accelerator design with time-sensitive affine typesRachit Nigam, Sachille Atapattu, Samuel Thomas, Zhijing Li 等PLDI 2020 · 被引用 58 次
- A compiler infrastructure for accelerator generatorsRachit Nigam, Samuel Thomas, Zhijing Li, Adrian SampsonASPLOS 2021 · 被引用 54 次
- Type-directed scheduling of streaming acceleratorsDavid Durst, Matthew Feldman, Dillon Huff, David Akeley 等PLDI 2020 · 被引用 49 次
- Modular Hardware Design with Timeline TypesRachit Nigam, Pedro Henrique Azevedo de Amorim, Adrian SampsonPLDI 2023 · 被引用 16 次
- HIR: An MLIR-based Intermediate Representation for Hardware Accelerator DescriptionKingshuk Majumder, Uday BondhugulaASPLOS 2023 · 被引用 12 次
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