Graph.hls: A Compiler Framework for Composable Graph Accelerator Design

FPGAs offer superior performance for graph processing, but existing High-Level Synthesis (HLS) frameworks face two critical bottlenecks: (1) optimization techniques scattered across incompatible frameworks cannot be composed-a simple 16-bit data type change requires modifying $200+$ lines across 10+files, and (2) developers lack systematic validation tools, forcing reliance on slow hardware emulation taking 50+minutes per iteration. We present Graph.hls, a domain- specific compiler framework that addresses these challenges through hierarchical abstraction and automated workflows. Graph.hls organizes graph accelerator parameters into three levels by modification cost, enabling composition of multiple optimizations through unified configuration. Graph.hls's GH-Architect automatically generates op- timized hardware by propagating dependencies and performing resource- aware code generation, while GH- Scope provides rapid verification through IR- level simulation and baseline comparison, completing validation in under 1 second. Our DSL naturally expresses graph algorithms beyond the traditional GAS model, and the hierarchical abstraction enables composing optimizations across algorithms and FPGA platforms without manual code integration. Evaluation shows Graph.hls achieves $2.6 \times$ average speedup over ReGraph and $1.2 \times$ over ThunderGP with fair parameter- matched comparison, and up to 4. 48× speedup with full multi- level design space exploration. GH- Scope accelerates simulation by 301. 6× over vendor C- Sim and reduces debugging time by up to 455, 000× over hardware emulation, enabling composable, high- performance graph accelerator design.