EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits
Jian Gao, Weimin Fu, Xiaolong Guo, Weidong Cao, Xuan Zhang
Abstract
Analog circuit design has traditionally depended on manual expertise, slowing the discovery of novel topologies essential for advanced technologies like AI, , and quantum computing. While AI-driven methods have accelerated hardware design workflows, most of them focus on topology synthesis, often reusing known structures to achieve specific goals. The challenge of discovering entirely new, high-performance topologies remains largely underexplored due to its abstract nature. In this work, we introduce EVA, an efficient and versatile generative engine for discovering novel analog circuit topologies. EVA employs a bottom-up generation framework, using a decoder-only transformer to sequentially predict device pin connections and create diverse circuits from scratch. Pretraining on unlabeled circuit topologies builds foundational knowledge about circuit connectivity, achieving baseline discovery efficiency by generating valid circuits and reducing performance-labeled samples needed in fine-tuning. For targeted discovery of highperformance designs, EVA leverages two fine-tuning strate-gies-proximal policy optimization (PPO) and direct preference optimization (DPO)-to further enhance discovery efficiency for relevant, high-performing topologies. Experimental results across various circuit types highlight EVA’s strengths in validity, novelty, versatility, and both training sample and discovery efficiency.
Ask about this paper
Ask your agent about it.
Lune has read the top-tier papers around this one, so every answer names the papers it rests on.
Your agent calls
Lunesearch_papers
Free to start. No credit card required.
Terminal
Install the CLIlune papers get 6e4ba46e-c337-47a0-a418-bf198a789f68Cited by top-tier papers1
Ask how each one uses itRelated papers
- AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit TopologiesJian Gao, Weidong Cao, Junyi Yang, Xuan ZhangICLR 2025
- AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology GenerationPrashanth Vijayaraghavan, Luyao Shi, Ehsan Degan, Vandana V. Mukherjee et al.ICML 2025
- Graph-Transformer-based Surrogate Model for Accelerated Converter Circuit Topology DesignShaoze Fan, Haoshu Lu, Shun Zhang, Ningyuan Cao et al.DAC 2024 · 9 citations
- AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph ModelingJian Gao, Weidong Cao, Xuan ZhangICML 2025
- LaMAGIC: Language-Model-based Topology Generation for Analog Integrated CircuitsChen-Chia Chang, Yikang Shen, Shaoze Fan, Jing Li et al.ICML 2024 · 39 citations
