ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis

Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, traditional accurate power simulation requires time-consuming back-end processing and simulation steps, which significantly impede design optimization. To address this, we propose ATLAS, which can predict the ultimate time-based layout power for any new design in the gate-level netlist. To the best of our knowledge, ATLAS is the first work that supports both time-based power simulation and general cross-design power modeling. It achieves such general timebased power modeling by proposing a new pre-training and fine-tuning paradigm customized for circuit power. Targeting golden per-cycle layout power from commercial tools, our ATLAS achieves the mean absolute percentage error (MAPE) of only 0.58%, 0.45%, and 5.12% for the clock tree, register, and combinational power groups, respectively, without any layout information. Overall, the MAPE for the total power of the entire design is <1%, and the inference speed of a workload is significantly faster than the standard flow of commercial tools. PRIMAL [DAC'20] APOLLO [MICRO'21] RTL Yes Yes No No Sengupta et al. [ICCAD'22] SNS [ISCA'22] SNS V2 [MICRO'23] No No Yes MasterRTL [ICCAD'23] Yes Yes PowPredicCT [DAC'24] Layout No ATLAS Netlist Yes Yes Yes Yes * GRANNITE estimates toggle rate instead of power, thus not listed in the table. It is neither time-based nor targeting layout.