ATR: Out-of-Order Register Release Exploiting Atomic Regions

Modern superscalar processors require large physical register files to support a high number of in-flight instructions, which is crucial for achieving higher ILP and IPC. Conventional register renaming techniques release physical registers conservatively, waiting until the instruction that redefines the same architectural register commits, which results in inefficient register utilization. In particular, registers frequently remain allocated for many cycles although they are no longer in-use. To address this deficiency, previous approaches have explored early register release, which aims to free registers as soon as they have been fully consumed. However, these techniques are either unsafe or conservative, limiting the benefits. We observe that over 17% of all allocated registers in SPEC2017int and 13% in SPEC2017fp are located within atomic commit regions, sequences that do not include conditional branches nor exception-causing instructions. Instructions within such regions are guaranteed to atomically commit or flush together, allowing safe early release of the registers allocated by the first instruction of a region. In particular, registers can be released without waiting for the redefining instruction of the architectural register to commit. We propose a novel renaming technique that leverages this insight to reduce register file pressure. Our technique enables out-of-order register release by identifying atomic commit regions using a simple mechanism that requires no stacks, queues, extra memory, or shadow cells. We show that, for SPEC2017int benchmarks, the proposed register renaming scheme achieves an average speedup of 5.13% for a 64-entry, and 1.48% for a 224-entry register file.