GLOVA: Global and Local Variation-Aware Analog Circuit Design with Risk-Sensitive Reinforcement Learning
Dongjun Kim, Junwoo Park, Chaehyeon Shin, Jaeheon Jung, Kyungho Shin, Seungheon Baek, Sanghyuk Heo, Woongrae Kim, In-Chul Jeong, Joohwan Cho, Jongsun Park
摘要
Analog/mixed-signal circuit design encounters significant challenges due to performance degradation from process, voltage, and temperature (PVT) variations. To achieve commercial-grade reliability, iterative manual design revisions and extensive statistical simulations are required. While several studies have aimed to automate variation-aware analog design to reduce time-to-market, the substantial mismatches in real-world wafers have not been thoroughly addressed. In this paper, we present GLOVA, an analog circuit sizing framework that effectively manages the impact of diverse random mismatches to improve robustness against PVT variations. In the proposed approach, risk-sensitive reinforcement learning is leveraged to account for the reliability bound affected by PVT variations, and ensemble-based critic is introduced to achieve sample-efficient learning. For design verification, we also propose μ-σ evaluation and simulation reordering method to reduce simulation costs of identifying failed designs. GLOVA supports verification through industrial-level PVT variation evaluation methods, including corner simulation as well as global and local Monte Carlo (MC) simulations. Compared to previous state-of-the-art variation-aware analog sizing frameworks, GLOVA achieves up to improvement in sample efficiency and reduction in time.
问问这篇 Paper
智能体会读完全文。
Lune 把这篇 Paper 索引到了每一个公式,引用它的顶会 Paper 也一样。你提问,回答直接引用原文。
它引用的顶会 Paper2
- GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement LearningHanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen 等DAC 2020 · 被引用 326 次
- Trust-Region Method with Deep Reinforcement Learning in Analog Design Space ExplorationKai-En Yang, Chia-Yu Tsai, Hung-Hao Shen, Chen-Feng Chiang 等DAC 2021 · 被引用 26 次
相关 Paper
- PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit SynthesisZichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du 等DAC 2024 · 被引用 17 次
- RoSE: Robust Analog Circuit Parameter Optimization with Sampling-Efficient Reinforcement LearningJian Gao, Weidong Cao, Xuan ZhangDAC 2023 · 被引用 19 次
- Priority-Based Graph-Enhanced Reinforcement Learning for Robust Analog Circuit OptimizationJintao Li, Zhenxin Chen, Sicheng He, Aojin Li 等AAAI 2026
- Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for SizingMinjeong Choi, Youngchang Choi, Kyongsu Lee, Seokhyeong KangDAC 2023 · 被引用 24 次
- DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural NetworksAhmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun 等DAC 2021 · 被引用 94 次
