GNN-assisted Back-side Clock Routing Methodology for Advance Technologies
Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto García Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim
摘要
The back-side metal layers exhibit lower parasitics compared to the front-side layers in advanced technologies, making them suitable for clock-net distribution. In this study, we explore the advantages of using back-side metal layers for clock routing, which is shared with a power delivery network. Our Graph Neural Network (GNN) based framework, effectively distributes the clock-tree between the front and back sides. We address the back-side clock nets' creation by incorporating back-side buffers. Our results demonstrate better clock and full-chip metrics represented by an increase of up to 13% in the effective frequency with equivalent power consumption, using 3 nm technology.
问问这篇 Paper
智能体会读完全文。
Lune 把这篇 Paper 索引到了每一个公式,引用它的顶会 Paper 也一样。你提问,回答直接引用原文。
引用它的顶会 Paper1
问问它们各自怎么用它相关 Paper
- GNN-MLS: Signal Routing in Mixed-Node 3D ICs through GNN-Assisted Metal Layer SharingJiawei Hu, Pruek Vanna-Iampikul, Zhen Zhuang, Tsung-Yi Ho 等DAC 2025 · 被引用 2 次
- SyncTREE: Fast Timing Analysis for Integrated Circuit Design through a Physics-informed Tree-based Graph Neural NetworkYuting Hu, Jiajie Li, Florian Klemme, Gi-Joon Nam 等NeurIPS 2023 · 被引用 12 次
- A timing engine inspired graph neural network model for pre-routing slack predictionZizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang 等DAC 2022 · 被引用 121 次
- Timing macro modeling with graph neural networksKevin Kai-Chun Chang, Chun-Yao Chiang, Pei-Yu Lee, Iris Hui-Ru JiangDAC 2022 · 被引用 6 次
- Bridging Layout and RTL: Knowledge Distillation based Timing PredictionMingjun Wang, Yihan Wen, Bin Sun, Jianan Mu 等ICML 2025
