MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design

A novel machine learning based parasitic estimation (MLParest) method for pre-layout custom circuit design is presented. It reduces the error between pre-layout and post-layout circuit simulation from 37% to 8% on average for different measurements across a variety of analog circuits. MLParest can thus greatly reduce the number of iterations between pre-layout and post-layout design phases. The key contributions of this work are a machine learning based approach to parasitic estimation and a push-button model training framework, scalable across different technology nodes. To the best of our knowledge, a machine learning based framework of parasitic estimation is an industry first.