A Hypervisor for Shared-Memory FPGA Platforms

Cloud providers widely deploy FPGAs as application-specifc accelerators for customer use. These providers seek to multiplex their FPGAs among customers via virtualization, thereby reducing running costs. Unfortunately, most virtualization support is confned to FPGAs that expose a restrictive, hostcentric programming model in which accelerators cannot issue direct memory accesses (DMAs). The host-centric model incurs high runtime overhead for workloads that exhibit pointer chasing. Thus, FPGAs are beginning to support a sharedmemory programming model in which accelerators can issue DMAs. However, virtualization support for shared-memory FPGAs is limited.

This paper presents OPTIMUS, the frst hypervisor that supports scalable shared-memory FPGA virtualization. OPTI-MUS offers both spatial multiplexing and temporal multiplexing to provide effcient and fexible sharing of each accelerator on an FPGA. To share the FPGA-CPU interconnect at a high clock frequency, OPTIMUS implements a multiplexer tree. To isolate each guest's address space, OPTIMUS introduces the technique of page table slicing as a hardware-software co-design. To support preemptive temporal multiplexing, OP-TIMUS provides an accelerator preemption interface. We show that OPTIMUS supports eight physical accelerators on a single FPGA and improves the aggregate throughput of twelve real-world benchmarks by 1.98x-7x.

• Software and its engineering Virtual machines.