R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII
Zewei Zhou, Jiajun Zou, Jiajia Zhang, Ao Yang, Ruichao He, Haozheng Zhou, Ao Liu, Jiawei Liu, Leilei Jin, Shan Shen, Daying Sun
摘要
Graph neural networks (GNNs) are increasingly applied to physical design tasks such as congestion prediction and wirelength estimation, yet progress is hindered by inconsistent circuit representations and the absence of controlled evaluation protocols. We present R2G (RTL-to-GDSII), a multi-view circuit-graph benchmark suite that standardizes five stage-aware views with information parity (every view encodes the same attribute set, differing only in where features attach) over 30 open-source IP cores (up to nodes/edges). R2G provides an end-to-end DEF-to-graph pipeline spanning synthesis, placement, and routing stages, together with loaders, unified splits, domain metrics, and reproducible baselines. By decoupling representation choice from model choice, R2G isolates a confound that prior EDA and graph-ML benchmarks leave uncontrolled. In systematic studies with GINE, GAT, and ResGatedGCN, we find: (i) view choice dominates model choice, with Test R varying by more than 0.3 across representations for a fixed GNN; (ii) node-centric views generalize best across both placement and routing; and (iii) decoder-head depth (3--4 layers) is the primary accuracy driver, turning divergent training into near-perfect predictions (R^2$$>0.99). Code and datasets are available at https://github.com/ShenShan123/R2G.
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它引用的顶会 Paper7
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- Versatile Multi-stage Graph Neural Network for Circuit RepresentationShuwen Yang, Zhihao Yang, Dong Li, Yingxue Zhang 等NeurIPS 2022 · 被引用 72 次
- CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design EnvironmentXun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin 等ICLR 2024 · 被引用 32 次
- CktGNN: Circuit Graph Neural Network for Electronic Design AutomationZehao Dong, Weidong Cao, Muhan Zhang, Dacheng Tao 等ICLR 2023 · 被引用 12 次
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