LHNN: lattice hypergraph neural network for VLSI congestion prediction
Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng
摘要
Precise congestion prediction from a placement solution plays a crucial role in circuit placement. This work proposes the lattice hypergraph (LH-graph), a novel graph formulation for circuits, which preserves netlist data during the whole learning process, and enables the congestion information propagated geometrically and topologically. Based on the formulation, we further developed a heterogeneous graph neural network architecture LHNN, jointing the routing demand regression to support the congestion spot classification. LHNN constantly achieves more than 35% improvements compared with U-nets and Pix2Pix on the F1 score. We expect our work shall highlight essential procedures using machine learning for congestion prediction.
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引用它的顶会 Paper14
- Versatile Multi-stage Graph Neural Network for Circuit RepresentationShuwen Yang, Zhihao Yang, Dong Li, Yingxue Zhang 等NeurIPS 2022 · 被引用 72 次
- CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design EnvironmentXun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin 等ICLR 2024 · 被引用 32 次
- Mitigating Distribution Shift for Congestion Optimization in Global PlacementSu Zheng, Lancheng Zou, Siting Liu, Yibo Lin 等DAC 2023 · 被引用 18 次
- A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip DesignZhihai Wang, Lei Chen, Jie Wang, Yinqi Bai 等ICML 2024 · 被引用 13 次
- PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware LearningYufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai 等DAC 2024 · 被引用 12 次
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