Bringing source-level debugging frameworks to hardware generators
Keyi Zhang, Zain Asgar, Mark Horowitz
摘要
High-level hardware generators have significantly increased the productivity of design engineers. They use software engineering constructs to reduce the repetition required to express complex designs and enable more composability. However, these benefits are undermined by a lack of debugging infrastructure, requiring hardware designers to debug generated, usually incomprehensible, RTL code. This paper describes a framework that connects modern software source-level debugging frameworks to RTL created from hardware generators. Our working prototype offers an Integrated Development Environment (IDE) experience for generators such as RocketChip (Chisel), allowing designers to set breakpoints in complex source code, relate RTL simulation state back to source-level variables, and do forward and backward debugging, with almost no simulation overhead (less than 5%).
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- RTL-Repair: Fast Symbolic Repair of Hardware Design CodeKevin Laeufer, Brandon Fajardo, Abhik Ahuja, Vighnesh Iyer 等ASPLOS 2024 · 被引用 14 次
- Stepwise Debugging for Hardware AcceleratorsGriffin Berlstein, Rachit Nigam, Christophe Gyurgyik, Adrian SampsonASPLOS 2023 · 被引用 2 次
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