CXL and the Return of Scale-Up Database Engines
Alberto Lerner, Gustavo Alonso
Abstract
The trend toward specialized processing devices such as TPUs, DPUs, GPUs, and FPGAs has exposed the weaknesses of PCIe in interconnecting these devices and their hosts. Several attempts have been proposed to improve, augment, or downright replace PCIe, and more recently, these efforts have converged into a standard called Compute Express Link (CXL). CXL is already on version 2.0 in terms of commercial availability, but its potential to radically change the conventional server architecture has only just started to surface. For example, CXL can increase the bandwidth and quantity of memory available to any single machine beyond what that machine can originally provide, most importantly, in a manner that is fully transparent to software applications.
We argue, however, that CXL can have a broader impact beyond memory expansion and deeply affect the architecture of data-intensive systems. In a nutshell, while the cloud favored scale-out approaches that grew in capacity by adding full servers to a rack, CXL brings back scale-up architectures that can grow by fine-tuning individual resources, all while transforming the rack into a large shared-memory machine. In this paper, we describe why such architectural transformations are now possible, how they benefit emerging heterogeneous hardware platforms for data-intensive systems, and the associated research challenges.
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Install the CLIlune papers fulltext 804d37a2-e59d-49a5-8e04-b518116a5d2eCited by top-tier papers6
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- Oasis: Pooling PCIe Devices Over CXL to Boost UtilizationYuhong Zhong, Daniel S. Berger, Pantea Zardoshti, Enrique Saurez et al.SOSP 2025 · 2 citations
- SIDLE: Tree-structure Aware Indexes for CXL-based Heterogeneous MemoryHaoru Zhao, Mingkai Dong, Fangnuo Wu, Haibo ChenVLDB 2026 · 1 citation
Builds on6
- Pond: CXL-Based Memory Pooling Systems for Cloud PlatformsHuaicheng Li, Daniel S. Berger, Lisa Hsu, Daniel Ernst et al.ASPLOS 2023 · 328 citations
- TPP: Transparent Page Placement for CXL-Enabled Tiered-MemoryHasan Al Maruf, Hao Wang, Abhishek Dhanotia, Johannes Weiner et al.ASPLOS 2023 · 255 citations
- Demystifying CXL Memory with Genuine CXL-Ready Systems and DevicesYan Sun, Yifan Yuan, Zeduo Yu, Reese Kuper et al.MICRO 2023 · 133 citations
- Pump Up the Volume: Processing Large Data on GPUs with Fast InterconnectsClemens Lutz, Sebastian Breß, Steffen Zeuch, Tilmann Rabl et al.SIGMOD 2020 · 99 citations
- The Case for Distributed Shared-Memory Databases with RDMA-Enabled Memory DisaggregationRuihong Wang, Jianguo Wang, Stratos Idreos, M. Tamer Özsu et al.VLDB 2023 · 49 citations
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- Exploring Performance and Cost Optimization with ASIC-Based CXL MemoryYupeng Tang, Ping Zhou, Wenhui Zhang, Henry Hu et al.EuroSys 2024 · 40 citations
- CXL Memory Performance for In-Memory Data ProcessingMarcel Weisgut, Daniel Ritter, Pinar Tözün, Lawrence Benson et al.VLDB 2025 · 7 citations
