Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue

Most Register Transfer Level (RTL) designs originate from behavioral descriptions specified in C or C++ often written by Software (SW) designers. Hardware (HW) designers then manually describe an efficient hardware implementation of that application using a Hardware Description Language (HDL) like Verilog or VHDL. Although it has been shown that High-Level Synthesis (HLS) provides a direct path to synthesizing these behavioral descriptions into RTL, the quality of the generated RTL is often still unacceptable, hence, requiring to manually design the HW. This is nevertheless time consuming and error prone. In particular, finding bugs introduced in the manual design is very tedious as HW designers rely on long simulations that generate large waveforms that have to be thoroughly scrutinized.