BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs
Martin Cochet, Karthik Swaminathan, Erik Jens Loscalzo, Joseph Zuckerman, Maico Cassel dos Santos, Davide Giri, Alper Buyuktosunoglu, Tianyu Jia, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose
Abstract
On-chip power-management techniques have evolved over several processor generations. However, response time and scalability constraints have made it difficult to translate existing power-management strategies to current or next-generation System-on-Chip (SoC) architectures, which are expected to comprise tens to hundreds of cores and accelerators. In this work we present BlitzCoin, a fully decentralized hardware power-management strategy for large, accelerator-rich SoCs, coupled with optimized unified voltage and frequency regulation. We evaluated BlitzCoin through RTL simulations of multiple SoCs targeted toward different application domains. The results are further validated through silicon measurements of a fabricated 12 nm many-accelerator SoC that includes BlitzCoin. Our evaluations show that BlitzCoin is markedly faster, with 8× to 12× lower response times, which provides 25%-34% throughput improvement and allows for scaling to 7 × to 13 × larger SoCs compared to state-of-the-art centralized power-management strategies, all with an area overhead of <1%.
Ask about this paper
Your agent reads all of it.
Lune indexed this paper to the last equation, along with the top-tier papers that cite it. Ask a question and the answer quotes them.
Builds on4
- SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile ProcessorsJawad Haj-Yahya, Mohammed Alser, Jeremie S. Kim, Abdullah Giray Yaglikçi et al.ISCA 2020 · 48 citations
- Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCsJoseph Zuckerman, Davide Giri, Jihye Kwon, Paolo Mantovani et al.MICRO 2021 · 24 citations
- AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server ApplicationsJawad Haj-Yahya, Haris Volos, Davide B. Bartolini, Georgia Antoniou et al.MICRO 2022 · 22 citations
- AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter ServersGeorgia Antoniou, Haris Volos, Davide B. Bartolini, Tom Rollet et al.MICRO 2022 · 6 citations
Related papers
- Area Bloating and the Future of SpecializationQixuan Yu, David WentzlaffHPCA 2026
- Centralized Training and Decentralized Control through the Actor-Critic Paradigm for Highly Optimized MulticoresBenedikt Dietrich, Heba Khdr, Jörg HenkelDAC 2025 · 2 citations
- PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNNJian Peng, Tingyuan Liang, Zhiyao Xie, Wei ZhangDAC 2023 · 1 citation
- ScalaGraph: A Scalable Accelerator for Massively Parallel Graph ProcessingPengcheng Yao, Long Zheng, Yu Huang, Qinggang Wang et al.HPCA 2022 · 30 citations
- NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End PerformanceTianyu Jia, Yuhao Ju, Russ Joseph, Jie GuMICRO 2020 · 21 citations
