Systematic CXL Memory Characterization and Performance Analysis at Scale
Jinshu Liu, Hamid Hadian, Yuyue Wang, Daniel S. Berger, Marie Nguyen, Xun Jian, Sam H. Noh, Huaicheng Li
Abstract
Compute Express Link (CXL) has emerged as a pivotal interconnect for memory expansion. Despite its potential, the performance implications of CXL across devices, latency regimes, processors, and workloads remain underexplored. We present Melody, a framework for systematic characterization and analysis of CXL memory performance. Melody builds on an extensive evaluation spanning 265 workloads, 4 real CXL devices, 7 latency levels, and 5 CPU platforms. Melody yields many insights: workload sensitivity to sub-μs CXL latencies (140-410ns), the first disclosure of CXL tail latencies, CPU tolerance to CXL latencies, a novel approach (SPA) for pinpointing CXL bottlenecks, and CPU prefetcher inefficiencies under CXL.
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Install the CLIlune papers fulltext 5528bf27-9101-45de-931e-47cb827fc30fCited by top-tier papers18
- Beluga: A CXL-Based Memory Architecture for Scalable and Efficient LLM KVCache ManagementXinjun Yang, Qingda Hu, Junru Li, Feifei Li et al.SIGMOD 2026 · 24 citations
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- Cylon: Fast and Accurate Full-System Emulation of CXL-SSDsDongha Yoon, Hansen Idden, Jinshu Liu, Berkay Inceisci et al.FAST 2026 · 6 citations
Builds on10
- Pond: CXL-Based Memory Pooling Systems for Cloud PlatformsHuaicheng Li, Daniel S. Berger, Lisa Hsu, Daniel Ernst et al.ASPLOS 2023 · 328 citations
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- Demystifying CXL Memory with Genuine CXL-Ready Systems and DevicesYan Sun, Yifan Yuan, Zeduo Yu, Reese Kuper et al.MICRO 2023 · 133 citations
- Managing Memory Tiers with CXL in Virtualized EnvironmentsYuhong Zhong, Daniel S. Berger, Carl A. Waldspurger, Ryan Wee et al.OSDI 2024 · 77 citations
- MEMTIS: Efficient Memory Tiering with Dynamic Page Classification and Page Size DeterminationTaehyung Lee, Sumit Kumar Monga, Changwoo Min, Young Ik EomSOSP 2023 · 67 citations
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