ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems

2 Please see §4.2 for the detailed methodology and observations. We study ColumnDisturb in great detail in §4 and §5.

flips than retention failures, and the number of ColumnDisturb bitflips is much higher than retention failures in all tested refresh intervals (i.e., 64ms, 128ms, 256ms, 512ms, and 1024ms) across all tested DRAM modules. For example, with a 512ms refresh interval and at 65 • C, ColumnDisturb induces 1.64x, 62.49x, and 152.66x more bitflips in 2, 6, and 232 more rows on average for tested SK Hynix, Micron, and Samsung modules, respectively, than retention failures.

Our observations show that ColumnDisturb has serious implications on the robustness of both 1) future systems and 2) existing retention-aware heterogeneous refresh mechanisms [75][76][77][78][79][80][81][82][83][84][85][86][87][88]. First, due to continuously shrinking DRAM node size, more ColumnDisturb bitflips may manifest in the standard refresh window in future DRAM chips, jeopardizing the robustness of future systems. We describe and evaluate two hardware techniques that could mitigate ColumnDisturb bitflips at varying expected performance, energy, and area overheads. A straightforward solution is to increase the DRAM refresh rate to accommodate ColumnDisturb bitflips that could happen in the standard refresh window. However, this straightforward solution reduces system throughput by 42.1% and increases system energy consumption by 67.5%. We instead propose to intelligently and timely refresh only the victim rows that are vulnerable to ColumnDisturb. We show that our improved solution reduces the straightforward solution's 1) system throughput overhead by 70.5% and 2) energy overhead by 73.8%. Second, we evaluate a retention-aware refresh mechanism (RAIDR) [76] and demonstrate that its benefits drastically decrease in the presence of ColumnDisturb (e.g., 53% decrease in performance) compared to a baseline RAIDR that does not suffer from ColumnDisturb.

We call for future research to 1) fundamentally understand ColumnDisturb at the device-level, 2) architect ColumnDisturbresilient, high-performance retention-aware refresh mechanisms, and3) other innovative solutions to mitigate Column-Disturb bitflips to enable ColumnDisturb-resilient, robust future computing systems.

This paper makes the following key contributions: • This is the first work to experimentally demonstrate a columnbased (i.e., bitline-based) read disturbance phenomenon in modern DRAM chips, ColumnDisturb, and its widespread existence in real DDR4 chips from all three major DRAM manufacturers and HBM2 chips from Samsung.

• We provide an extensive experimental characterization of ColumnDisturb on 216 real DDR4 and 4 HBM2 DRAM chips. ColumnDisturb induces bitflips across three subarrays (e.g., 3072 rows), greatly more than RowHammer & RowPress that affect only a few rows in a single subarray.

• Our experimental results show that ColumnDisturb 1) gets worse as DRAM technology scales down to smaller cell sizes, 2) already induces bitflips within a standard refresh window in some existing DRAM chips, and 3) induces significantly more bitflips in many more rows than retention failures, for a given refresh interval.

• We describe and evaluate two solutions to ColumnDisturb for future DRAM-based systems.

• We evaluate a retention-aware heterogeneous refresh mechanism (RAIDR [76]) and show that ColumnDisturb can completely diminish the performance and energy benefits of such mechanisms.