Rosebud: Making FPGA-Accelerated Middlebox Development More Pleasant

We introduce an approach to designing FPGA-accelerated middleboxes that simplifies development, debugging, and performance tuning by decoupling the tasks of hardware-accelerator implementation and software-application programming. Rosebud is a framework that links hardware accelerators to a high-performance packet processing pipeline through a standardized hardware/software interface. This separation of concerns allows hardware developers to focus on optimizing custom accelerators while freeing software programmers to reuse, configure, and debug accelerators in a fashion akin to software libraries. We show the benefits of the Rosebud framework by building a firewall based on a large blacklist and porting the Pigasus IDS pattern-matching accelerator in less than a month. Our experiments demonstrate that Rosebud delivers high performance, serving ∼200 Gbps of traffic while adding only 0.7-7 microseconds of latency. This work makes the following contributions:

• The RPU abstraction facilitates software-based development and debugging for FPGA-accelerated middleboxes.

• We implement the Rosebud framework for load balancing middlebox workloads across packet processors, enabling coarse parallelism and no-pause reconfiguration.

• We demonstrate that these development tools can be used to build 200-Gbps middleboxes much faster than with existing tools by porting the hardware accelerators of a state-of-theart IDS to Rosebud, and making a firewall, in only one month.