μManycore: A Cloud-Native CPU for Tail at Scale
Jovan Stojkovic, Chunao Liu, Muhammad Shahbaz, Josep Torrellas
摘要
Microservices are emerging as a popular cloud-computing paradigm. Microservice environments execute typically-short service requests that interact with one another via remote procedure calls (often across machines), and are subject to stringent tail-latency constraints. In contrast, current processors are designed for traditional monolithic applications. They support global hardware cache coherence, provide large caches, incorporate microarchitecture for long-running, predictable applications (such as advanced prefetching), and are optimized to minimize average latency rather than tail latency.
To address this imbalance, this paper proposes 𝜇Manycore, an architecture optimized for cloud-native microservice environments. Based on a characterization of microservice applications, 𝜇Manycore is designed to minimize unnecessary microarchitecture and mitigate overheads to reduce tail latency. Indeed, rather than supporting manycore-wide hardware cache coherence, 𝜇Manycore has multiple small hardware cache-coherent domains, called Villages. Clusters of villages are interconnected with an on-package leaf-spine network, which has many redundant, low-hop-count paths between clusters. To minimize latency overheads, 𝜇Manycore schedules and queues service requests in hardware, and includes hardware support to save and restore process state when doing a context-switch. Our simulation-based results show that 𝜇Manycore delivers high performance. A cluster of 10 servers with a 1024-core 𝜇Manycore in each server delivers 3.7× lower average latency, 15.5× higher throughput, and, importantly, 10.4× lower tail latency than a cluster with iso-power conventional server-class multicores. Similar good results are attained compared to a cluster with power-hungry iso-area conventional server-class multicores.
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引用它的顶会 Paper6
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- Mosaic: Harnessing the Micro-Architectural Resources of Servers in Serverless EnvironmentsJovan Stojkovic, Esha Choukse, Enrique Saurez, Íñigo Goiri 等MICRO 2024 · 被引用 6 次
- Harvesting Memory-bound CPU Stall Cycles in Software with MSHZhihong Luo, Sam Son, Sylvia Ratnasamy, Scott ShenkerOSDI 2024 · 被引用 5 次
- HardHarvest: Hardware-Supported Core Harvesting for MicroservicesJovan Stojkovic, Chunao Liu, Muhammad Shahbaz, Josep TorrellasISCA 2025 · 被引用 4 次
它引用的顶会 Paper19
- Catalyzer: Sub-millisecond Startup for Serverless Computing with Initialization-less BootingDong Du, Tianyi Yu, Yubin Xia, Binyu Zang 等ASPLOS 2020 · 被引用 280 次
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- Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement LearningRahul Bera, Konstantinos Kanellopoulos, Anant Nori, Taha Shahroodi 等MICRO 2021 · 被引用 95 次
- Kite: A Family of Heterogeneous Interposer Topologies Enabled via Accurate Interconnect ModelingSrikant Bharadwaj, Jieming Yin, Bradford M. Beckmann, Tushar KrishnaDAC 2020 · 被引用 94 次
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