SkyByte: Architecting an Efficient Memory-Semantic CXL-based SSD with OS and Hardware Co-design
Haoyang Zhang, Yuqi Xue, Yirui Eric Zhou, Shaobo Li, Jian Huang
摘要
The CXL-based solid-state drive (CXL-SSD) provides a promising approach towards scaling the main memory capacity at low cost. However, the CXL-based SSD faces performance challenges due to the long flash access latency and unpredictable events such as garbage collection in the SSD device, stalling the host processor and wasting compute cycles. Although the CXL interface enables the byte-granular data access to the SSD, accessing flash chips is still at page granularity due to physical limitations. The mismatch of access granularity causes significant unnecessary I/O traffic to flash chips, worsening the suboptimal end-to-end data access performance. In this paper, we present SkyByte, an efficient CXL-based SSD that employs a holistic approach to address the aforementioned challenges by co-designing the host operating system (OS) and SSD controller. To alleviate the long memory stall when accessing the CXL-SSD, SkyByte revisits the OS context switch mechanism and enables opportunistic context switches upon the detection of long access delays. To accommodate byte-granular data accesses, SkyByte architects the internal DRAM of the SSD controller into a cacheline-level write and a page-level data cache, and enables data coalescing upon log cleaning to reduce the I/O traffic to flash chips. SkyByte also employs optimization techniques that include adaptive page migration for exploring the performance benefits of fast host memory by promoting hot pages in CXL-SSD to the host. We implement SkyByte with a CXL-SSD simulator and evaluate its efficiency with various data-intensive applications. Our experiments show that SkyByte outperforms current CXL-based SSD by , and reduces the I/O traffic to flash chips by on average. SkyByte also reaches of the performance of the ideal case that assumes unlimited DRAM capacity in the host, which offers an attractive cost-effective solution.
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引用它的顶会 Paper3
- Cylon: Fast and Accurate Full-System Emulation of CXL-SSDsDongha Yoon, Hansen Idden, Jinshu Liu, Berkay Inceisci 等FAST 2026 · 被引用 6 次
- Harvesting Sub-Microsecond CXL Memory Stalls with LiteSwitchNanqinqin Li, Yuhong Zhong, Asaf Cidon, Michael J. FreedmanOSDI 2026
- Espresso: Constructing Cost-Efficient CXL JBOF via Inter-SSD Computing Resource SharingShushu Yi, Yuda An, Li Peng, Xiurui Pan 等OSDI 2026
它引用的顶会 Paper14
- Pond: CXL-Based Memory Pooling Systems for Cloud PlatformsHuaicheng Li, Daniel S. Berger, Lisa Hsu, Daniel Ernst 等ASPLOS 2023 · 被引用 328 次
- TPP: Transparent Page Placement for CXL-Enabled Tiered-MemoryHasan Al Maruf, Hao Wang, Abhishek Dhanotia, Johannes Weiner 等ASPLOS 2023 · 被引用 255 次
- Demystifying CXL Memory with Genuine CXL-Ready Systems and DevicesYan Sun, Yifan Yuan, Zeduo Yu, Reese Kuper 等MICRO 2023 · 被引用 133 次
- Managing Memory Tiers with CXL in Virtualized EnvironmentsYuhong Zhong, Daniel S. Berger, Carl A. Waldspurger, Ryan Wee 等OSDI 2024 · 被引用 77 次
- Overcoming the Memory Wall with CXL-Enabled SSDsShao-Peng Yang, Minjae Kim, Sanghyun Nam, Juhyung Park 等USENIX ATC 2023 · 被引用 75 次
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