DiffTest-H: Toward Semantic-Aware Communication in Hardware-Accelerated Processor Verification

Verification has become the most time-consuming phase in chip development. Co-simulation frameworks simulate the design under test (DUT) with a golden reference model (REF) and compare their instruction-level results for verification, causing over 98% communication overhead: although hardware-accelerated platforms, such as FPGA and emulators, speed up DUT simulation by 300×-10000×, overall co-simulation speedup is still limited to 2.5×-20×.

In this paper, we propose DiffTest-H, a semantic-aware, hardwareaccelerated co-simulation framework with three techniques reducing communication overhead while preserving debuggability: (1) Batch minimizes communication frequency by tightly packing structurally diverse verification events into a single transfer.

(2) Squash reduces data transmission volume by fusing verification events with a decoupled checking order. (3) Replay preserves instruction-level debuggability by reprocessing the original, unfused verification events around the failure point.

DiffTest-H is deployed on both Palladium emulator and FPGA to verify a 6-wide, out-of-order RISC-V processor, XiangShan. It achieves simulation speeds of 478KHz and 7.8MHz respectively, with an 80× and 78× speedup over the baseline, 119× and 1945× faster than 16-thread Verilator, and uncovers 151 bugs in XiangShan.