Bumper: Hinting Instruction Usefulness for Robust Unified Caches

Contemporary mobile applications exhibit large instruction working sets that overwhelm cores' front-end structures, leading to frequent pipeline stalls that significantly harm performance. We find that a key contributor to the front-end bottleneck is code pollution in the unified L2 cache (L2C) stemming from a high incidence of fetches and prefetches on the wrong execution path. Such wrong-path allocations waste, on average, 20% of a large L2C's capacity with instruction cache lines that are useless - i.e., lines that are evicted from the cache before any of the instructions they contain ever commits. This work demonstrates that tracking whether a code line contains committed instructions provides a robust foundation for code-aware cache management. Building on this insight, we propose Bumper, a lightweight microarchitectural scheme that dynamically propagates usefulness hints based on commit information to the cache hierarchy and selectively prioritizes useful code lines in the L2C, enabling rapid eviction of useless lines. The principal challenge addressed in the design of Bumper is how to orchestrate the propagation of usefulness hints based on commit information across the CPU pipeline and cache hierarchy, while minimizing microarchitectural overheads. Using an industry-grade simulator, we show that Bumper mitigates the front-end bottleneck of real-world mobile applications by reducing L2C code pollution and improving the lifetime of useful code lines, outperforming state-of-the-art schemes by over 5.4%, on average, at a storage cost of just 422 bytes.