Elevating Temporal Prefetching Through Instruction Correlation

Temporal prefetchers can learn from irregular memory accesses and hide access latencies.As the on-chip storage technology for temporal prefetchers' metadata advances, enabling the development of viable commercial prefetchers, it becomes evident that the precious on-chip storage resources highlight a significant deficiency in the existing temporal prefetchers' utilization of metadata.This paper introduces Kairos, which actively prefetches address with repetitive characteristics by detecting critical memory access instructions and tracking the prefetch coverage of corresponding metadata.Kairos operates on two principles: Temporal prefetchers are designed based on a program's repetitive memory access behaviors, (1) allowing for the filtering out of instructions with low access probability to eliminate interference from corresponding temporal metadata; (2) retaining metadata with high prefetch potential while discarding low-utility entries.Kairos achieves a 25.2% overall speedup compared to a baseline system with an IP-stride prefetcher, and outperforms state-of-theart Triangel by 10.1%, while reducing storage overhead by two orders of magnitude, demonstrating substantially higher performance at significantly lower cost.