Reconfigurable Quantum Instruction Set Computers for High Performance Attainable on Hardware

Despite remarkable milestones in quantum computing, the performance of current quantum hardware remains limited. One critical path to higher performance is to expand the quantum ISA with basis gates that have higher fidelity and greater synthesis capabilities than the standard CNOT. However, this substantially increases gate calibration overhead and introduces challenges in compiler optimization. Consequently, although more expressive ISAs (even complex, continuous gate sets) have been proposed, they still remain primarily proofs-of-concept and have not been widely adopted.

To move beyond these hurdles and unlock the performance gains offered by expressive continuous ISAs, we introduce the concept of "reconfigurable quantum instruction set computers" (ReQISC). It incorporates (1) a unified microarchitecture capable of directly implementing arbitrary 2Q gates equivalently, i.e., SU(4) modulo 1Q rotations, with theoretically optimal gate durations given any 2Q coupling Hamiltonian and (2) a compilation framework tailored to Re-QISC primitives for end-to-end synthesis and optimization, comprising a program-aware pass that refines high-level representations, a program-agnostic pass for aggressive circuitlevel optimization, and an SU(4)-aware routing pass that minimizes hardware mapping overhead.

We detail the hardware implementation to demonstrate the feasibility of this superior gate scheme in terms of both pulse control and calibration. By leveraging the expressivity of SU(4) and the time minimality realized by the underlying microarchitecture, the SU(4)-based ISA achieves remarkable performance, with a 4.97-fold reduction in average pulse duration to implement arbitrary 2Q gates, compared to the usual CNOT/CZ scheme on mainstream flux-tunable transmons. Supported by the end-to-end compiler, ReQISC outperforms the conventional CNOT-based ISA, state-of-the-art