Sensitivity Importance Sampling Yield Analysis and Optimization for High Sigma Failure Rate Estimation

The impact of process variation to advanced integrated circuits has become increasingly significant. Traditional sampling based yield analysis and optimization always require large amount of expensive simulations. This paper proposes an All Sensitivity Adversarial Importance Sampling (ASAIS) yield optimization method, which avoids samplings in outer optimization based on sensitivity. Moreover, Fast Sensitivity Importance Sampling (FSIS) yield analysis method is adopted as inner yield analysis to eliminate the sampling using transient sensitivity analysis. Experiments on SRAM show ASAIS generates more than 90X speedup of the entire yield optimization process, while FSIS speedup 3X-I5X over existing methods.