AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling

Power efficiency is a critical design objective in modern CPU design. Architects need a fast yet accurate architecture-level power evaluation tool to perform early-stage power estimation. However, traditional analytical architecture-level power models are inaccurate. The recently proposed machine learning (ML)-based architecture-level power model requires sufficient data from known configurations for training, making it unrealistic.

In this work, we propose AutoPower targeting fully automated architecture-level power modeling with limited known design configurations. We have two key observations: (1) The clock and SRAM dominate the power consumption of the processor, and (2) The clock and SRAM power correlate with structural information available at the architecture level. Based on these two observations, we propose the power group decoupling in AutoPower. First, AutoPower decouples across power groups to build individual power models for each group. Second, AutoPower designs power models by further decoupling the model into multiple sub-models within each power group. In our experiments, AutoPower can achieve a low mean absolute percentage error (MAPE) of 4.36% and a high R 2 of 0.96 even with only two known configurations for training. This is 5% lower in MAPE and 0.09 higher in R 2 compared with McPAT-Calib, the representative ML-based power model.

Engineers carefully analyze the hardware behavior of each component when relevant events occur to infer the activity of the hardware circuit, and then utilize their own experience and experimental data to estimate the power consumption of the component when relevant events occur.