Mirror Asymmetry Perfect Hashing: A Memory-Efficient and Load-Intensive-Optimized Hashing Index on Hybrid DRAM-PMem Architecture

The increasing demand for high-performance key-value (KV) stores has driven the adoption of hierarchical memory architectures combining fast DRAM with persistent memory (PMem). Current solutions struggle to balance high load factors with high write performance and low DRAM overhead. This arises from the PMem-DRAM speed gap, which makes PMemside collision resolution a performance bottleneck, and mitigating this often requires maintaining more complex DRAM-side mapping metadata. This paper proposes Mirror Asymmetry Perfect Hashing (MAPH), a cuckoo hashing-based hybrid DRAM-PMem KV store with a dynamic perfect hashing index, that achieves DRAM-only collision resolution through asymmetric position decoupling across memory tiers, enabling high load factors with minimal DRAM metadata overhead. Our approach simultaneously achieves high load factors, low latency, and high concurrent throughput. Experimental evaluation demonstrates $\mathbf{2. 8} \times-\mathbf{1 3. 6} \times$ lower latency and significantly higher throughput than state-ofthe-art solutions, while incurring lower DRAM space overhead and competitive PMem efficiency.