Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization

Though using multi-bit flip-flop (MBFF) cells provide the benefit of saving dynamic power, its big cell size with many D/Q-pins inherently entails two critical limitations, which are (1) the loss of full flexibility in optimizing the wires connecting to the D/Q-pins in MBFFs and (2) the loss of selectively resizing i.e., controlling the driving strength of internal flip-flops in MBFFs to optimize timing. In this work, we propose a comprehensive solution to resolving those limitations through design and technology co-optimization (DTCO) in physical design flow. Specifically, to address limitation 1, given an input circuit with MBFF allocation and binding, at the post-placement stage we explore diverse layouts of MBFF cells with various D/Q-pin locations and rebind MBFF instances in the circuit to the MBFF cells that are the most suitable for minimizing the wirelength connecting D/Q-pins. Meanwhile, to address limitation 2, at the post-route stage we explore MBFF cell layouts of non-rectangle, precisely, L- and T-shape to control the driving strength of internal flip-flops selectively, by which we rebind MBFF instances with negative slack to the area-minimal rectangle or non-rectangle MBFF cells to optimize timing while increasing the power overhead minimally. Through experiments with benchmark circuits, it is shown that our DTCO driven MBFF rebinding method is able to produce the circuit implementations with 1.42% less wirelength in comparison with that produced by the state-of-the-art commercial EDA tool using MBFFs.