Mitigating Routability Problems in Complementary-FET-based VLSI Designs

As semiconductor technology scales beyond 5 nm, complementary FET (CFET) that stacks P-FET and N-FET enables extreme cell area scaling. However, reduced standard cell height with CFET presents routability challenges due to limited back-end-of-line (BEOL) routing resources. In this paper, we address two key routability problems, i.e., pin accessibility and routing congestion, by employing various pin-extended cells on demand. Moreover, we introduce an end-to-end VLSI design framework that further alleviates routing congestion using partial placement blockages. Experimental results demonstrate that our framework eliminates most design rule violations (DRVs) related to routability while maintaining the area advantages of CFET technology.