Alternate Path μ-op Cache Prefetching
Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros
摘要
Datacenter applications are well-known for their large code footprints. This has caused frontend design to evolve by implementing decoupled fetching and large prediction structures - branch predictors, Branch Target Buffers (BTBs) - to mitigate the stagnating size of the instruction cache by prefetching instructions well in advance. In addition, many designs feature a micro operation (-op) cache, which primarily provides power savings by bypassing the instruction cache and decoders once warmed up. However, this -op cache often has lower reach than the instruction cache, and it is not filled up speculatively using the decoupled fetcher. As a result, the -op cache is often over-subscribed by datacenter applications, up to the point of becoming a burden. This paper first shows that because of this pressure, blindly prefetching into the -op cache using state-of-the-art standalone prefetchers would not provide significant gains. As a consequence, this paper proposes to prefetch only critical -ops into the op cache, by focusing on execution points where the -op cache provides the most gains: Pipeline refills. Concretely, we use hardto-predict conditional branches as indicators that a pipeline refill is likely to happen in the near future, and prefetch into the -op cache the -ops that belong to the path opposed to the predicted path, which we call alternate path. Identifying hard-to-predict branches requires no additional state if the branch predictor confidence is used to classify branches. Including extra alternate branch predictors with limited budget (8.95 KB to 12.95 KB), our proposal provides average speedups of to and as high as on a subset of CVP-1 traces.
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引用它的顶会 Paper3
- Rethinking Prefetching for Intermittent ComputingGan Fang, Jianping Zeng, Aditya Gupta, Changhee JungISCA 2025 · 被引用 5 次
- From Optimal to Practical: Efficient Micro-op Cache Replacement Policies for Data Center ApplicationsKan Zhu, Yilong Zhao, Yufei Gao, Peter Braun 等HPCA 2025 · 被引用 3 次
- Assassyn: A Unified Abstraction for Architectural Simulation and ImplementationJian Weng, Boyang Han, Derui Gao, Ruijie Gao 等ISCA 2025 · 被引用 1 次
它引用的顶会 Paper10
- I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op CachesXida Ren, Logan Moody, Mohammadkazem Taram, Matthew Jordan 等ISCA 2021 · 被引用 59 次
- Twig: Profile-Guided BTB Prefetching for Data Center ApplicationsTanvir Ahmed Khan, Nathan Brown, Akshitha Sriraman, Niranjan K. Soundararajan 等MICRO 2021 · 被引用 33 次
- A Cost-Effective Entangling Prefetcher for InstructionsAlberto Ros, Alexandra JimboreanISCA 2021 · 被引用 31 次
- Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict BranchesStephen Pruett, Yale N. PattMICRO 2021 · 被引用 23 次
- UC-Check: Characterizing Micro-operation Caches in x86 Processors and Implications in Security and PerformanceJoonsung Kim, Hamin Jang, Hunjun Lee, Seungho Lee 等MICRO 2021 · 被引用 15 次
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