VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code

Modern chip design is complex, and there is a crucial need for early-stage prediction of key design-quality metrics like timing and routing congestion directly from Verilog code (a commonly used programming language for hardware design). It is especially important yet complex to predict individual lines of code that cause timing violations or downstream routing congestion. Prior works have tried approaches like converting Verilog into an intermediate graph representation and using LLM embeddings alongside other features to predict module-level quality, but did not consider line-level quality prediction. We propose VeriLoC, the first method that predicts design quality directly from Verilog at both the line-and module-level. To this end, VeriLoC leverages recent Verilog codegeneration LLMs to extract local line-level and module-level embeddings, and trains downstream classifiers/regressors on concatenations of these embeddings. VeriLoC achieves high F1-scores of 0.86-0.95 for line-level congestion and timing prediction, and reduces the mean average percentage error from 14% -18% for SOTA methods down to only 4%. We believe that VeriLoC embeddings and insights from our work will also be of value for other predictive and optimization tasks for complex hardware design. * Both authors contributed equally to this research. 2 HDL codes are commonly also referred to as register-transfer level (RTL) descriptions. We use RTL or Verilog interchangeably from here on. 39th Conference on Neural Information Processing Systems (NeurIPS 2025).