A2: Analog Malicious Hardware
Kaiyuan Yang, Matthew Hicks, Qing Dong, Todd M. Austin, Dennis Sylvester
摘要
While the move to smaller transistors has been a boon for performance it has dramatically increased the cost to fabricate chips using those smaller transistors. This forces the vast majority of chip design companies to trust a third partyoften overseas-to fabricate their design. To guard against shipping chips with errors (intentional or otherwise) chip design companies rely on post-fabrication testing. Unfortunately, this type of testing leaves the door open to malicious modifications since attackers can craft attack triggers requiring a sequence of unlikely events, which will never be encountered by even the most diligent tester. In this paper, we show how a fabrication-time attacker can leverage analog circuits to create a hardware attack that is small (i.e., requires as little as one gate) and stealthy (i.e., requires an unlikely trigger sequence before effecting a chip's functionality). In the open spaces of an already placed and routed design, we construct a circuit that uses capacitors to siphon charge from nearby wires as they transition between digital values. When the capacitors fully charge, they deploy an attack that forces a victim flip-flop to a desired value. We weaponize this attack into a remotely-controllable privilege escalation by attaching the capacitor to a wire controllable and by selecting a victim flip-flop that holds the privilege bit for our processor. We implement this attack in an OR1200 processor and fabricate a chip. Experimental results show that our attacks work, show that our attacks elude activation by a diverse set of benchmarks, and suggest that our attacks evade known defenses.
问问这篇 Paper
智能体会读完全文。
Lune 把这篇 Paper 索引到了每一个公式,引用它的顶会 Paper 也一样。你提问,回答直接引用原文。
引用它的顶会 Paper20
- Inferring Fine-grained Control Flow Inside SGX Enclaves with Branch ShadowingSangho Lee, Ming-Wei Shih, Prasun Gera, Taesoo Kim 等USENIX Security 2017 · 被引用 536 次
- ZeroTrace : Oblivious Memory Primitives from Intel SGXSajin Sasy, Sergey Gorbunov, Christopher W. FletcherNDSS 2018 · 被引用 244 次
- ICAS: an Extensible Framework for Estimating the Susceptibility of IC Layouts to Additive TrojansTimothy Trippel, Kang G. Shin, Kevin B. Bush, Matthew HicksS&P 2020 · 被引用 35 次
- ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement LearningVasudev Gohil, Hao Guo, Satwik Patnaik, Jeyavijayan RajendranCCS 2022 · 被引用 34 次
- Static Detection of Unsafe DMA Accesses in Device DriversJia-Ju Bai, Tuo Li, Kangjie Lu, Shi-Min HuUSENIX Security 2021 · 被引用 28 次
相关 Paper
- Silicon Heist: (Ransom) Attacks for Cloud FPGAs via Privilege EscalationSimon Klix, Felix Hahn, Maik Ender, Nils Albartus 等USENIX Security 2026
- DELTA: DEsigning a stealthy trigger mechanism for analog hardware trojans and its detection analysisNishant Gupta, Mohil Sandip Desai, Mark Wijtvliet, Shubham Rai 等DAC 2022 · 被引用 6 次
- Rethinking IC Layout Vulnerability: Simulation-Based Hardware Trojan Threat Assessment with High FidelityXinming Wei, Jiaxi Zhang, Guojie LuoS&P 2024 · 被引用 7 次
- Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided AttacksNimisha Limaye, Animesh Basak Chowdhury, Christian Pilato, Mohammed Thari Nabeel 等DAC 2021 · 被引用 28 次
- GDSII-Guard: ECO Anti-Trojan Optimization with Exploratory Timing-Security Trade-OffsXinming Wei, Jiaxi Zhang, Guojie LuoDAC 2023 · 被引用 9 次
