Efficient and scalable core multiplexing with M³v

The M 3 system (ASPLOS '16) proposed a hardware/software codesign that simplifies integration between general-purpose cores and special-purpose accelerators, allowing users to easily utilize them in a unified manner. M 3 is a tiled architecture, whose tiles (cores and accelerators) are partitioned between applications, such that each tile is dedicated to its own application.

The M 3 x system (ATC '19) extended M 3 by trading off some isolation to enable coarse-grained multiplexing of tiles among multiple applications. With M 3 x, if source tile 𝑡 1 runs code of application 𝑝 and sends a message 𝑚 to destination tile 𝑡 2 while 𝑡 2 is currently not associated with 𝑝, then 𝑚 is forwarded to the right place through a łslow pathž, via some special OS tile.

In this paper, we present M 3 v, which extends M 3 x by further trading off some isolation between applications to support łfast pathž communication that does not require the said OS tile's involvement. Thus, with M 3 v, a tile can be efficiently multiplexed between applications provided it is a general-purpose core. M 3 v achieves this goal by 1) adding a local multiplexer to each such core, and by 2) virtualizing the core's hardware component responsible for cross-tile communications. We prototype M 3 v using RISC-V cores on an FPGA platform and show that it significantly outperforms M 3 x and may achieve competitive performance to Linux.