BlueFace: Integrating an Accelerator into the Core's Pipeline through Algorithm-Interface Co-Design for Real-Time SoCs

In modern real-time heterogeneous System-on-Chips, ensuring real-time performance is increasingly important. However, with ever-increasing hardware and architectural complexity, satisfying such timing requirements becomes very challenging due to both hardware heterogeneity and the complicated access paths induced by the on-chip accelerators. In this paper, inspired by an interesting observation from accelerable real-time task scheduling, we propose a new core-accelerator interface, BlueFace, which is integrated into the memory access stage of the CPU pipeline, effectively avoiding the complicated HA access paths. The BlueFace design constructs a priority queue to schedule the HA operations at the hardware level, ensuring simultaneous throughput and real-time performance. The evaluation demonstrates the performance benefits and gives the overhead of BlueFace.