Understanding the Host Network
Midhul Vuppalapati, Saksham Agarwal, Henry Schuh, Baris Kasikci, Arvind Krishnamurthy, Rachit Agarwal
2024Year
25Citations
10Top-tier citations
Abstract
The host network integrates processor, memory, and peripheral interconnects to enable data transfer within the host. Several recent studies from production datacenters show that contention within the host network can have significant impact on end-to-end application performance. The goal of this paper is to build an in-depth understanding of such contention within the host network.
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Install the CLIlune papers get cd75455c-9738-42cc-ae77-9e3a4504f329Cited by top-tier papers10
- Tiered Memory Management: Access Latency is the Key!Midhul Vuppalapati, Rachit AgarwalSOSP 2024 · 22 citations
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- Understanding and Profiling CXL.mem Using PathFinderXiao Li, Zerui Guo, Yuebin Bai, Mahesh Ketkar et al.SIGCOMM 2025 · 6 citations
- Building A CSFQ-Inspired Transport for Switched CXL Memory PoolingZerui Guo, Emily Shriver, Ming LiuNSDI 2026 · 2 citations
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