Unrealizable Cores for Reactive Systems Specifications
Shahar Maoz, Rafi Shalom
Abstract
One of the main challenges of reactive synthesis, an automated procedure to obtain a correct-by-construction reactive system, is to deal with unrealizable specifications. One means to deal with unrealizability, in the context of GR(1), an expressive assume-guarantee fragment of LTL that enables efficient synthesis, is the computation of an unrealizable core, which can be viewed as a fault-localization approach. Existing solutions, however, are computationally costly, are limited to computing a single core, and do not correctly support specifications with constructs beyond pure GR(1) elements. In this work we address these limitations. First, we present QuickCore, a novel algorithm that accelerates unrealizable core computations by relying on the monotonicity of unrealizability, on an incremental computation, and on additional properties of GR(1) specifications. Second, we present Punch, a novel algorithm to efficiently compute all unrealizable cores of a specification. Finally, we present means to correctly handle specifications that include higher-level constructs beyond pure GR(1) elements. We implemented our ideas on top of Spectra, an open-source language and synthesis environment. Our evaluation over benchmarks from the literature shows that QuickCore is in most cases faster than previous algorithms, and that its relative advantage grows with scale. Moreover, we found that most specifications include more than one core, and that Punch finds all the cores significantly faster than a competing naive algorithm.
Ask about this paper
Your agent reads all of it.
Lune indexed this paper to the last equation, along with the top-tier papers that cite it. Ask a question and the answer quotes them.
Your agent calls
Luneget_paper_fulltext
Free to start. No credit card required.
Terminal
Install the CLIlune papers fulltext be5be9a1-027c-4a60-a134-a0918c226a25Cited by top-tier papers4
- Using Reactive Synthesis: An End-to-End Exploratory Case StudyDor Ma'ayan, Shahar MaozICSE 2023 · 10 citations
- Which of My Assumptions are Unnecessary for Realizability and Why Should I Care?Rafi Shalom, Shahar MaozICSE 2023 · 6 citations
- Dynamic Update for Synthesized GR(1) ControllersGal Amram, Shahar Maoz, Itai Segall, Matan YossefICSE 2022 · 4 citations
- Evolution-Aware Heuristics for GR(1) Realizability CheckingDor Ma'ayan, Shahar Maoz, Jan Oliver RingertASE 2025 · 1 citation
Builds on1
Related papers
- Performance Heuristics for GR(1) Unrealizable Core ComputationShachaf Cohen, Shahar MaozFM 2026
- Efficient Incremental GR(1) Synthesis via Monotonic Fixed-Point ReuseSirui Liu, Wei Dong, Yijie Zheng, Haonan GuoOOPSLA 2026
- Just-In-Time Reactive SynthesisShahar Maoz, Ilia ShevrinASE 2020 · 12 citations
- Triggers for Reactive Synthesis SpecificationsGal Amram, Dor Ma'ayan, Shahar Maoz, Or Pistiner et al.ICSE 2023 · 6 citations
- Full LTL Synthesis over Infinite-State ArenasShaun Azzopardi, Luca Di Stefano, Nir Piterman, Gerardo SchneiderCAV 2025 · 9 citations
