Exploiting Hidden Resource Contention in Selective Speculation Defenses

Transient execution attacks continue to evolve beyond cache-centric channels, motivating selective speculation defenses that aim to provide comprehensive protection with low overhead by delaying only transmit instructions. In this work, we show that several state-of-the-art selective-speculation defenses rest on shared assumptions that overlook important microarchitectural behaviors, leaving systematic blind spots that admit secret-dependent reservation-station (RS) contention. Our analysis identifies three limitations in optimized selective-speculation designs. First, existing transmit taxonomies emphasize post-issue execution effects and miss dispatch-phase channels, such as operand-dependent μop expansion in instructions (e.g., REP-prefixed string operations) that create operand-dependent RS occupancy before execution. Second, the delay-until-resolution strategy focuses on redirect-based control leakage, but predicated instructions (e.g., x86 CMOV and RISC-V Zicond) enable secret-dependent selection without branch resolution, allowing secrets to steer operand-dependent μop expansion (e.g., REP iteration counts). Finally, the older-μop-first allocation strategy assumes unsafe contention is prevented by prioritizing non-transient μops, yet undelayed arithmetic and cache-hit memory μops can still lead to secret-dependent RS pressure through latency-amplifying dependency chains. Guided by these findings, we construct Spectre-v1-style gadgets that bypass STT/DOLMA on x86 and RISC-V gem5 models. We further validate RS-contention effects on real CPUs, including a REP MOVSB- and REP STOSB-based proof-of-concept and a real-world RS-contention pattern identified by our LLVM pass, demonstrating realistic gadget structure and measurable signal. Finally, we propose strengthened STT mechanisms that close both existing and newly exposed gaps at moderate performance overhead.