Securator: A Fast and Secure Neural Processing Unit
Nivedita Shrivastava, Smruti Ranjan Sarangi
Abstract
Securing deep neural networks (DNNs) is a problem of significant interest since an ML model incorporates high-quality intellectual property, features of data sets painstakingly collated by mechanical turks, and novel methods of training on large cluster computers. Sadly, attacks to extract model parameters are on the rise, and thus designers are being forced to create architectures for securing such models. State-of-the-art proposals in this field take the deterministic memory access patterns of such networks into cognizance (albeit partially), group a set of memory blocks into a tile, and maintain state at the level of tiles (to reduce storage space). For providing integrity guarantees (tamper avoidance), they don’t propose any significant optimizations, and still maintain block-level state.We observe that it is possible to exploit the deterministic memory access patterns of DNNs even further, and maintain state information for only the current tile and current layer, which may comprise a large number of tiles. This reduces the storage space, reduces the number of memory accesses, increases performance, and simplifies the design without sacrificing any security guarantees. The key techniques in our proposed accelerator architecture, Securator, are to encode memory access patterns to create a small HW-based tile version number generator for a given layer, and to store layer-level MACs. We completely eliminate the need for having a MAC cache and a tile version number store (as used in related work). We show that using intelligently-designed mathematical operations, these structures are not required. By reducing such overheads, we show a speedup of 20.56% over the closest competing work.
Ask about this paper
Your agent reads all of it.
Lune indexed this paper to the last equation, along with the top-tier papers that cite it. Ask a question and the answer quotes them.
Your agent calls
Luneget_paper_fulltext
Free to start. No credit card required.
Terminal
Install the CLIlune papers fulltext 7b7065c1-e3c5-4c99-bf9a-5018a7c9c44cCited by top-tier papers6
- sNPU: Trusted Execution Environments on Integrated NPUsErhu Feng, Dahu Feng, Dong Du, Yubin Xia et al.ISCA 2024 · 13 citations
- TensorTEE: Unifying Heterogeneous TEE Granularity for Efficient Secure Collaborative Tensor ComputingHusheng Han, Xinyao Zheng, Yuanbo Wen, Yifan Hao et al.ASPLOS 2024 · 12 citations
- Adaptive CHERI Compartmentalization for Heterogeneous AcceleratorsJianyi Cheng, A. Theodore Markettos, Alexandre Joannou, Paul Metzger et al.ISCA 2025 · 4 citations
- SeDA: Secure and Efficient DNN Accelerators with Hardware/Software SynergyWei Xuan, Zhongrui Wang, Lang Feng, Ning Lin et al.DAC 2025 · 3 citations
- SoK: Analysis of Accelerator TEE DesignsChenxu Wang, Junjie Huang, Yujun Liang, Xuanyao Peng et al.NDSS 2026 · 2 citations
Builds on6
- DarKnight: An Accelerated Framework for Privacy and Integrity Preserving Deep Learning Using Trusted HardwareHanieh Hashemi, Yongqin Wang, Murali AnnavaramMICRO 2021 · 51 citations
- TNPU: Supporting Trusted Execution with Tree-less Integrity Protection for Neural Processing UnitSunho Lee, Jungwoo Kim, Seonjin Na, Jongse Park et al.HPCA 2022 · 37 citations
- Common Counters: Compressed Encryption Counters for Secure GPU MemorySeonjin Na, Sunho Lee, Yeonjae Kim, Jongse Park et al.HPCA 2021 · 34 citations
- GuardNN: secure accelerator architecture for privacy-preserving deep learningWeizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward SuhDAC 2022 · 28 citations
- SEALing Neural Network Models in Encrypted Deep Learning AcceleratorsPengfei Zuo, Yu Hua, Ling Liang, Xinfeng Xie et al.DAC 2021 · 18 citations
Related papers
- MGX: near-zero overhead memory protection for data-intensive acceleratorsWeizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward SuhISCA 2022 · 27 citations
- Welder: Scheduling Deep Learning Memory Access via Tile-graphYining Shi, Zhi Yang, Jilong Xue, Lingxiao Ma et al.OSDI 2023 · 64 citations
- NASGuard: A Novel Accelerator Architecture for Robust Neural Architecture Search (NAS) NetworksXingbin Wang, Boyan Zhao, Rui Hou, Amro Awad et al.ISCA 2021 · 9 citations
- AutoSkewBMT: Autonomously Synthesizing Optimized Integrity Authentication Mechanism for DNN AcceleratorsRakin Muhammad Shadab, Sanjay Gandham, Mingjie LinDAC 2025
- DeepHardMark: Towards Watermarking Neural Network HardwareJoseph Clements, Yingjie LaoAAAI 2022 · 10 citations
