MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors
Zhe Jiang, Minli Liao, Sam Ainsworth, Dean You, Timothy M. Jones
Abstract
Heterogeneous parallel error detection is an approach to achieving fault-tolerant processors, leveraging multiple power-efficient cores to re-execute software originally run on a high-performance core. Yet, its complex components, gathering data cross-chip from many parts of the core, raise questions of how to build it into commodity cores without heavy design invasion and extensive re-engineering. We build the first full-RTL design, MEEK, into an open-source SoC, from microarchitecture and ISA to the OS and programming model. We identify and solve bottlenecks and bugs overlooked in previous work, and demonstrate that MEEK offers microsecond-level detection capacity with affordable overheads. By trading off architectural functionalities across codesigned hardware-software layers, MEEK features only light changes to a mature out-of-order superscalar core, simple coordinating software layers, and a few lines of operating-system code. The Repo. of MEEK’s source code: https://github.com/SEU-ACAL/reproduce-MEEK-DAC-25
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Builds on3
- AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoCFrancesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgiomaria Cicero et al.DAC 2020 · 47 citations
- ParaDox: Eliminating Voltage Margins via Heterogeneous Fault ToleranceSam Ainsworth, Lionel Zoubritzky, Alan Mycroft, Timothy M. JonesHPCA 2021 · 7 citations
- BlueScale: a scalable memory architecture for predictable real-time computing on highly integrated SoCsZhe Jiang, Kecheng Yang, Neil C. Audsley, Nathan Fisher et al.DAC 2022 · 3 citations
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