DRAM Fault Classification through Large-Scale Field Monitoring for Robust Memory RAS Management

As DRAM technology scales down, maintaining prior levels of reliability becomes increasingly challenging due to heightened susceptibility to faults.This growing concern underscores the need for effective in-field fault monitoring and management.Addressing this challenge, this work first introduces a refined DRAM fault classification, derived from the correlation between DRAM addresses and their underlying architectural hierarchies of faulty DRAMs.Building on this classification, we propose a comprehensive memory fault management strategy adequate to each DRAM fault.We further formalize and implement a structured remediation framework, enabling fault-specific mitigation.Utilizing this methodology, we conduct a large-scale field study on DDR4 x4 and DDR5 10x4 RDIMMs, uncovering that over 98% of DDR4 x4 RDIMM faults are tightly coupled with intra-bank architectural characteristics.In particular, we identify that early detection and localized management of faults within 2×2 MATs 1 -encompassing the vast majority of clustered row faults-are crucial to achieving resilient memory subsystems.We also observe intrinsic correlations among faulty Row Addresses (RAs), indicating unavoidable structural address 1 More rigorous definition on MAT will be discussed in §4.1.