AutoSizer: Automatic Sizing of Analog and Mixed-Signal Circuits via Large Language Model (LLM) Agents
Xi Yu, Dmitrii Torbunov, Soumyajit Mandal, Yihui Ren
Abstract
The design of Analog and Mixed-Signal (AMS) integrated circuits remains heavily reliant on expert knowledge, with transistor sizing a major bottleneck due to nonlinear behavior, highdimensional design spaces, and strict performance constraints. Existing Electronic Design Automation (EDA) methods typically frame sizing as static black-box optimization, resulting in inefficient and less robust solutions. Although Large Language Models (LLMs) exhibit strong reasoning abilities, they are not suited for precise numerical optimization in AMS sizing. To address this gap, we propose AUTOSIZER, a reflective LLM-driven meta-optimization framework that unifies circuit understanding, adaptive searchspace construction, and optimization orchestration in a closed loop. It employs a two-loop optimization framework, with an inner loop for circuit sizing and an outer loop that analyzes optimization dynamics and constraints to iteratively refine the search space from simulation feedback. We further introduce AMS-SIZINGBENCH, an open benchmark comprising 24 diverse AMS circuits in SKY130 CMOS technology, designed to evaluate adaptive optimization policies under realistic simulator-based constraints. AUTOSIZER experimentally achieves higher solution quality, faster convergence, and higher success rate across varying circuit difficulties, outperforming both traditional optimization methods and existing LLMbased agents. Our code is available at https:// github.com/yuxi120407/AutoSizer .
Ask about this paper
Your agent reads all of it.
Lune indexed this paper to the last equation, along with the top-tier papers that cite it. Ask a question and the answer quotes them.
Your agent calls
Luneget_paper_fulltext
Free to start. No credit card required.
Terminal
Install the CLIlune papers fulltext 26050f25-ddb9-4e36-910f-0befb89cf0d9Builds on8
- SWE-bench: Can Language Models Resolve Real-world Github Issues?Carlos E. Jimenez, John Yang, Alexander Wettig, Shunyu Yao et al.ICLR 2024 · 2,082 citations
- AgentVerse: Facilitating Multi-Agent Collaboration and Exploring Emergent BehaviorsWeize Chen, Yusheng Su, Jingwei Zuo, Cheng Yang et al.ICLR 2024 · 594 citations
- GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement LearningHanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen et al.DAC 2020 · 326 citations
- DS-Agent: Automated Data Science by Empowering Large Language Models with Case-Based ReasoningSiyuan Guo, Cheng Deng, Ying Wen, Hechang Chen et al.ICML 2024 · 107 citations
- Local Bayesian Optimization For Analog Circuit SizingKonstantinos Touloupas, Nikos Chouridis, Paul P. SotiriadisDAC 2021 · 31 citations
Related papers
- AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology GenerationPrashanth Vijayaraghavan, Luyao Shi, Ehsan Degan, Vandana V. Mukherjee et al.ICML 2025
- AnalogVerifier: A Neuro-Symbolic Framework for Analog Circuit VerificationYanfang Liu, Mingjun Wang, Peng XU, Rongliang Fu et al.ICML 2026
- Artisan: Automated Operational Amplifier Design via Domain-specific Large Language ModelZihao Chen, Jiangli Huang, Yiting Liu, Fan Yang et al.DAC 2024 · 30 citations
- AnalogCoder: Analog Circuit Design via Training-Free Code GenerationYao Lai, Sungyoung Lee, Guojin Chen, Souradip Poddar et al.AAAI 2025 · 105 citations
- Can LLMs Reason About Program Semantics? A Comprehensive Evaluation of LLMs on Formal Specification InferenceThanh Le-Cong, Bach Le, Toby MurrayACL 2025
