OASIS: A Commercial High Performance Terminal AI Processor Supporting RISC-V Tensor Extension Instructions

The exponential growth of artificial intelligence (AI) has spurred a demand for efficient, scalable computing.While domain-specific accelerators (DSAs) outperform general-purpose GPUs, their closed architectures lead to ecosystem fragmentation.The open RISC-V ISA offers a path to a unified ecosystem, but faces fundamental architectural challenges: the inefficiency of standard extensions for domain-specific workloads and severe memory contention in heterogeneous SoCs.This paper investigates these challenges and proposes a set of evidence-backed design principles for highperformance RISC-V AI accelerators.To this end, we present OA-SIS, the first commercial terminal AI processor supporting RISC-V tensor extension instructions.Its core innovation is a scalable, multi-core RISC-V Tensor Processing Unit (RTPU) architected with three key principles: a hardware-accelerated data path to solve the im2col bottleneck; a decoupled memory subsystem to eliminate resource contention; and a novel, low-overhead synchronization mechanism that enables near-linear multi-core scaling.The success of this evidence-driven architecture is ultimately validated by an evaluation of the fabricated chip.To demonstrate its versatility, we benchmark its performance across a wide spectrum of representative AI models.Our results consistently show superior performance over leading commercial platforms across key terminal AI scenarios.This outcome is supported by deep-dive analyses including multi-core scaling and multi-model concurrency tests, alongside a Roofline model which confirms high hardware utilization.