Exploiting Burstiness to Improve Multi-Core Interference Analysis

In the never-ending quest for performance, multicore processors include a variety of hardware-managed performance-improving components. In this paper, we are mostly interested in components pertaining to the memory subsystem, like prefetch queues, caches, or complex arbiters. We study the case where such components generate or take into account memory access bursts. We show how an explicit modeling of memory traffic burstiness allows significant improvements in the precision of interference analysis. We provide both the formal apparatus for modeling burstiness and dedicated analysis algorithms. Evaluation is performed on one of the few high-performance shared-memory architectures that is welldocumented - the Kalray MPPA3 Coolidge many-core, where our method covers one compute cluster.