Shortest Path to Secured Hardware: Domain Oriented Masking with High-Level-Synthesis
Rajat Sadhukhan, Sayandeep Saha, Debdeep Mukhopadhyay
Abstract
Implementing hardware secure against side-channel attacks (SCA) demands significant time and expertise in hardware design. In this paper, we propose a simple and fast approach for synthesizing masked block cipher hardware from a C-code exploiting High-Level-Synthesis (HLS), which allows a very short design time. Compared to previous approaches, our proposal provides a systematic and general flow based on state-of-the-art Domain-Oriented Masking (DOM). We also present a fast security-validation flow for the synthesized circuits at the early design stages using commercial-off-the-shelf CAD tools. Efficacy of the proposed design-flow has been established over a set of representative benchmarks including a masked S-Box and a lightweight block-cipher.
Ask about this paper
Ask your agent about it.
Lune has read the top-tier papers around this one, so every answer names the papers it rests on.
Your agent calls
Lunesearch_papers
Free to start. No credit card required.
Terminal
Install the CLIlune papers get 1d8408a6-f69a-48c4-a2a9-6f9e021db3f8Related papers
- HyCaMi: High-Level Synthesis for Cache Side-Channel MitigationHeiko Mantel, Joachim Schmidt, Thomas Schneider, Maximilian Stillger et al.DAC 2024 · 1 citation
- INDIANA - Verifying (Random) Probing Security Through Indistinguishability AnalysisChristof Beierle, Jakob Feldtkeller, Anna Guinet, Tim Güneysu et al.EUROCRYPT 2025 · 2 citations
- Low-Latency Hardware Private CircuitsDavid Knichel, Amir MoradiCCS 2022 · 20 citations
- It's About Time: Detecting Timing Side-Channel Vulnerabilities in High-Level Synthesis DesignsDenis Zuppiger, Katharina Ceesay-Seitz, Jiahui Xu, Lana Josipović et al.CCS 2026
- On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic CircuitsKazuki Monta, Makoto Nagata, Josep Balasch, Ingrid VerbauwhedeDAC 2023 · 3 citations
