Matrix‑PIC: Harnessing Matrix Outer-product for High‑Performance Particle‑in‑Cell Simulations

Particle-in-Cell (PIC) simulations devote most cycles to particle-grid interactions, and their fine-grained atomic updates become a severe bottleneck on traditional many-core CPUs. The evolution of CPU architectures, particularly the integration of specialized Matrix Processing Units (MPUs) designed for efficient matrix outer-product operations, presents a paradigm shift and an opportunity to alleviate these bottlenecks. Capitalizing on this architectural advancement, this work focuses on adapting the critical current deposition step in PIC simulations to this new matrix-centric computational model.

We introduce MatrixPIC, a novel framework representing, to our knowledge, the first holistic co-design of the deposition kernel, data layout, and an incremental sorting mechanism, all tailored specifically for the hybrid MPU-VPU SIMD execution model on modern CPUs. It provides a validated design paradigm for the scientific computing community to leverage the next generation of high-density hardware.

The key technical innovations are: (i) the refactoring of the current deposition algorithm into block-matrix updates that map efficiently onto the MPU's native operational paradigm; (ii) a hybrid execution pipeline that synergistically orchestrates MPU kernels for high-density accumulation with VPU stages for data preparation and control flow; and (iii) an 𝑂 (1)-amortized incremental particle sorter, which utilizes a gapped packed-memory array to establish and maintain the crucial data locality required for MPU efficiency.