A Bitstream Reverse Engineering Tool for FPGA Hardware Trojan Detection

Since FPGAs are field-programmable and reconfigurable integrated circuits, there are many security concerns that malicious functions like hardware Trojans can be infiltrated into circuits not only in development stages but also in deployment stages -- malicious fabrication and modification are possible even after deployment. To detect hardware Trojans effectively, we must be able to deal with the netlists available at development stages and the bitstreams available at deployment stages -- it is highly desired to reverse-engineer the bitstreams to the netlists, but unfortunately greatly challenging. In this poster, we introduce our project aiming at hardware Trojans detection at both stages in FPGAs, and present our bitstream reverse engineering tool called BRET, recently developed for Xilinx Virtex-5 bitstreams. We also discuss the prospective results and directions.